Advanced FPGA Designs

Blue Pearl Software Inc. provides products that automate the generation of timing constraints, validate existing timing constraints and check functional design issues at the functional or register transfer level (RTL) of the digital chip design flow. Blue Pearl’s software is used by ASIC and FPGA designers early in the design flow, on high-level functional design descriptions of an integrated circuit (IC), to develop higher quality RTL code and to automatically generate comprehensive and accurate timing constraints that significantly improve quality of results (QoR).